Microcontrollers associated with watchdog timers are known in the prior art. External interference or unexpected logic conditions can sometimes cause failure of an application or software used by the microcontroller. The closer controllers are located to strong magnetic and electrical fields, the more they are subject to such failures. The application or the software then fails to operate in accordance with its normal logic sequence.
Watchdog timers conventionally have a register with several bits which store a remaining time period before a reset. The bits are decremented at regular intervals by a timer, in the form of a countdown. When the microcontroller operates normally, the micro-controller writes a non-zero time period at regular intervals in the register. In most cases of abnormal microcontroller operation, the application or software runs in a loop and no longer writes any new time value in the register of the watchdog timer. The countdown therefore continues until it times out.
On timeout, the watchdog timer resets the microcontroller. For this purpose, one of the register bits is logically connected to a microcontroller reset pin. When this bit reaches a low status, i.e., on expiration of the time limit, the microcontroller is reset. The application or software used on the microcontroller can then be restarted under good conditions. A logic circuit can also be inserted between the register bit intended for resetting and the reset pin of the microcontroller. The logic circuit can be an ET or NON-ET type and have a second input connected to a logic activation input. The functioning of the watchdog timer can therefore be activated or disabled selectively via this circuit.
This type of watchdog timer has disadvantages. The software or application of the microcontroller may unduly write new time periods at reduced time intervals in the register of the watchdog timer. This may be the case, in particular, if the application or software of the microcontroller runs in an endless loop on a write routine in the register of the watchdog timer. Therefore, even in the event of failure of the application or program, the register does not undergo countdown to timeout and the application or software is therefore not reset.
Also, U.S. Pat. No. 4,705,970 describes a watchdog timer for a microprocessor. The timer has two counters. The counters are respectively associated with a minimum time period and a maximum time period separating two successive timer refresh commands. These two counters are fully independent. This timer has the disadvantage of two close refresh commands causing resetting of the microprocessor, whereas they do not necessarily correspond to a software loop.